1. Field of the Invention
The present invention relates to a memory system which combines a multilevel NAND flash EEPROM type nonvolatile memory having a large capacity but limited in program sequence of a page in a block, an FeRAM having a medium capacity but capable of high-speed read/write, and a controller for controlling these memories, and which apparently gives randomness to page programming in a block of the multilevel NAND flash EEPROM type nonvolatile memory, thereby greatly improving the performance of random write applications such as an OS operation.
2. Description of the Related Art
Semiconductor memories are presently widely used in many apparatuses such as main memories of mainframe and personal computers, household electric appliances, and cellphones. Those which are predominate in the market are flash EEPROM type nonvolatile memories represented by a NAND flash memory, and various types of memory cards (SD card, MMC card, MS card, and CF card) are used as media for storing information such as still images, motion images, sounds, and games in storage media of, e.g., digital cameras, digital videos, music players such as MP3, mobile PC's, and digital TV. USB compatible cards are also extensively used as storage media of PCs.
The flash EEPROM type nonvolatile memories are roughly classified into a NOR memory and NAND memory. The NOR memory can perform high-speed write, and can also perform read about 1013 times. This NOR memory is used to store instruction codes in a mobile gear. However, the NOR memory is unsuitable for file recording because the effective bandwidth of write is small.
On the other hand, the NAND memory can be highly integrated compared to the NOR memory. Although the access time is as long as 25 μs, burst read can be performed, and the effective bandwidth is large. Also, the program time and erase time of write are as long as 200 μs and about 1 ms, respectively, but a large number of bits can be programmed or erased at once. This makes it possible to load write data in a burst manner and program a large number of bit pages at once. Therefore, the NAND memory is a memory having a large effective bandwidth. By making the most of these advantages, the NAND memories are used in memory cards and USB memories as described above, and are recently used in memories of cellphones.
FIG. 1 shows a circuit diagram of a memory cell block of a NAND flash EEPROM, and a block diagram of a cell array of the same. Since memory cells are arranged one by one at the intersections of word lines WL0, WL1, . . . , WL7 and bit lines BL0, BL1, . . . , BL3, this memory is most suitable for high integration. A plurality of floating gate type transistors are connected in series, and selection transistors are arranged on the side of the bit lines BL0, BL1, . . . , BL3, and on the side of a source line SL.
In the above arrangement, a unit for performing erase is a memory cell block unit in the upper portion of FIG. 1 when viewed in the bit direction, and is one entire mat in the lower portion of FIG. 1 when viewed in the word line direction, and the erase unit is divided by a capacity of about 256 KB. This erase unit is called a block.
A program unit corresponds to one word line in the erase block and every other bit line (an even-numbered bit line EvenBL or odd-numbered bit line OddBL). When the number of series-connected cells is 32, the program unit is 256 KB/32/2=4 KB. This program unit is called a page. In this example, the block/page ratio is 64. One of the odd-numbered bit lines OddBL and even-numbered bit lines EvenBL is read in a read operation as well. When the even-numbered bit line EvenBL is to be read, for example, the odd-numbered bit line OddBL is set at Vss in order to reduce the interference noise between them.
FIGS. 2A to 2D illustrate examples of read, program, and erase operations of the NAND flash memory. In the read operation, as shown in FIG. 2A, the word line of a cell to be read is set at 0V, and the rest is changed to High. If a threshold voltage Vt of the cell transistor is Vt>0, the BL changes to Low. If Vt<0, the BL stays High, and the cell data is read out.
In the erase operation, as shown in FIG. 2D, the well potential of the whole cell block is set at 20V, and the rest is set at 0V, thereby drawing electrons of the floating gate to the well by a tunneling current to make the threshold voltage Vt lower than 0V. Accordingly, the erase unit is a large unit of 256 KB.
As shown in FIG. 2B, the program operation is performed by respectively setting the word line and bit line of a selected cell at 20V and 0V, thereby raising the threshold voltage by injecting electrons into the floating gate by a tunneling current.
In this state, as shown in FIG. 2C, the word line of each unselected cell in the same block is set at about 7V to decrease the applied voltage to a unselected transistor and suppress write. For a bit not to be written of the selected word line, the bit line is set at 7V, and a unselected word line is raised to 7V to boot the source and drain voltages of the cell transistor to about 10V, thereby suppressing write. This example is a binary method which stores 1-bit information in one cell. Recently, however, a four-valued method which stores 2-bit information in one cell is beginning to be used.
FIG. 3 shows a case in which four values are given to the threshold voltage of a cell transistor in one cell. In the first programming, 1 or 0 is written in a lower bit. In the second programming, an upper bit is written. This gives the four threshold voltage distributions. Although this quaternary method is suited to increasing the density, the threshold voltage Vt of the cell transistor must be suppressed to the distribution within a narrow range. This makes the program time and erase time longer than those of the binary method. In addition, a read operation requires determination at least twice, so it takes a long time to start reading out data.
As described above, the multilevel NAND flash EEPROM type nonvolatile memory has a lower operating speed and tighter allowable threshold voltage distribution than those of the binary memory.
FIGS. 4A and 4B each show the internal node potential of a block connected to an unselected bit line in a selected block. As shown in FIG. 4A, when data is to be programmed in a cell connected to one word line in the block, no problem arises if a cell closer to a bit line than the selected cell is kept erased. However, as shown in FIG. 4B, when no data is to be programmed in an unselected cell connected to one selected word line in the block, if a cell closer to a bit line than the unselected cell is already programmed, the threshold voltage of each memory cell transistor changes, and this changes the capacitance of an inverting layer. As a consequence, the source and drain potentials of the cell to be booted change.
More specifically, after a bit line is set at 7V and 7V are applied to a block select line on the bit line side, if a word line connected to a cell other than a selected cell is set at 7V, clamping occurs at the threshold voltage of a block select transistor, and the source-drain node of each transistor is booted. This boot potential fluctuates in accordance with the value of programming of an unselected cell. In this case, the source potential of a cell which is connected to a selected word line and is not to be programmed largely fluctuates. Consequently, this cell is weakly programmed to cause an operation error in a read operation.
On the other hand, a cell closer to the source line than the selected word line is not programmed but safely protected by setting the word line at 0V. To avoid this problem, write must be performed in the direction from the source line to the bit line in the multilevel NAND flash EEPROM type nonvolatile memory. That is, the order of pages to be programmed in a block must be fixed or limited.
Accordingly, although data can be written page by page by using the multilevel NAND flash EEPROM type nonvolatile memory, the order of pages is limited, so no random data write is possible. As a consequence, data can be written only block by block.
One solution to the problem of the NAND flash as described above is a ferroelectric memory (to be referred to as an FeRAM hereinafter) capable of high-speed read/write as a storage medium similarly to a DRAM, and also capable of storing information even when the power supply is turned off. In addition to the ability to perform high-speed read/write, the ferroelectric memory can be rewritten 1013 to 1016 times, has a read/write time equivalent to that of a DRAM, and can operate at 3 to 5V. The ferroelectric memory having these advantages is also called an ultimate memory. The use of the ferroelectric memory can solve the problem of slow read/write of the NAND flash.
Unfortunately, the FeRAM is presently not so highly integrated as the NAND flash, and therefore incurs a high cost.
The FeRAM will be briefly explained below. FIG. 5A shows a memory cell having one transistor and one capacitor of a conventional ferroelectric memory. In this memory cell of the conventional ferroelectric memory, the transistor and capacitor are connected in series. A cell array includes a bit line BL for reading out data, word lines WL0 and WL1 for selecting a memory cell transistor, and plate lines PL0 and PL1 for driving one terminal of the ferroelectric capacitor.
In this conventional ferroelectric memory, however, to prevent destruction of polarization information in the ferroelectric capacitor of an unselected cell, the plate lines are disconnected by the word lines and must be individually driven. Accordingly, a driving circuit of the plate lines PL0 and PL1 is as very large as 20% to 30% of the chip size, and the plate line driving time is long.
To solve the above problem, the present inventors have proposed a new nonvolatile ferroelectric memory capable of simultaneously achieving (1) a small memory cell, (2) a readily fabricable planar transistor, and (3) a versatile high-speed random access function, in Jpn. Pat. Appln. KOKAI Publication Nos. H10-255483, H11-177036, and 2000-22010 as prior applications.
FIG. 5B shows the arrangement of this ferroelectric memory of the above prior applications. In the prior applications, one memory cell is formed by connecting a cell transistor and ferroelectric capacitor in parallel, and one memory cell block is formed by connecting a plurality of parallel circuits of memory cells in series. One terminal of the block is connected to a bit line BL via a block select transistor, and the other terminal of the block is connected to a plate line PL.
The operation is as follows. In a standby state, all word lines WL0, WL1, . . . , WL3 are changed to High to turn on the memory cell transistors, and a block select signal BS is changed to Low to turn off the block select transistor. Since the two terminals of the ferroelectric capacitor are electrically shorted by the ON cell transistor, no potential difference is produced between them, so the stored polarization is stably held.
In an active state, only a memory cell transistor connected in parallel to a ferroelectric capacitor to be read is turned off, and the block select transistor is turned on. After that, the plate line PL and block select signal BS are changed to High. Accordingly, the potential difference between the plate line PL and bit line BL is applied only to the two terminals of a ferroelectric capacitor connected in parallel to the OFF memory cell transistor, so polarization information of this ferroelectric capacitor is read out to the bit line. Although the cells are connected in series, therefore, cell information of a given ferroelectric capacitor is read out by selecting a given word line, so complete random access can be realized. Also, since the plate line PL can be shared by a plurality of memory cells, it is possible to increase the area of a plate line driving circuit (PL driver) while the chip size is reduced, and to realize a high-speed operation.
In addition, the present inventors have proposed a ferroelectric memory capable of an ultra-high-speed operation in Jpn. Pat. Appln. KOKAI Publication No. 2004-263383. In this memory, as shown in FIG. 5C, a ferroelectric capacitor and cell transistor are connected in series to form each cell, and a plurality of cells are connected in parallel. A reset transistor is further connected in parallel to this parallel circuit, and the obtained parallel circuit is connected to a bit line via a block select transistor. This ferroelectric memory can achieve the effects of the prior applications described above, and can also further increase the operating speed by the effect of connecting the series circuits of cells in parallel. This is so because in the standby state, it is possible to short circuit all ferroelectric caps via the reset transistor by turning on all the cell transistors, and to share the plate driving line, unlike in the conventional ferroelectric memory.
An MRAM is also proposed as a nonvolatile memory capable of high-speed read/write. This MRAM is a memory in which a thin film of, e.g., Al2O3 is sandwiched by magnetic layers, and an electric current in the thin film increases if the spin directions in the upper and lower magnetic layers are the same, and reduces if the spin directions are opposite. This difference gives the memory a binary value. Although the MRAM is capable of high-speed read/write similarly to the FeRAM, the chip size is larger and the cost is higher than those of the NAND flash. A phase change memory (also called a PRAM) having a relatively short write time is also proposed, but the cost of this memory is also high.